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never stop thinking. hyb25dc512800c[e/f] HYB25DC512160C[e/f] 512-mbit double-data-rate sdram ddr sdram rohs compliant products data sheet, rev. 1.10, oct. 2005 memory products .com .com .com 4 .com u datasheet
edition 2005-10 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. .com .com .com .com 4 .com u datasheet template: mp_a4_s_rev314 / 3 / 2005-05-02 hyb25dc512800c[e/f], HYB25DC512160C[e/f] revision history: 2005-10 , rev. 1.10 previous version: 2005-08, rev. 1.00 page subjects (major cha nges since last revision) 9 added product types hyb25dc5128 00c[e/f]-6 and HYB25DC512160C[e/f]-6 65 addded ac timing diagrams 69 added i dd currents ddr333 we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send us your proposal (including a reference to this document) to: techdoc.mp@infineon.com .com .com .com .com 4 .com u datasheet data sheet 4 rev. 1.10, 2005-10 hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.3 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.4 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.1 dll enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.2 output drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5.1 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5.2 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5.3 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5.4 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.5.5 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.6 input clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.6 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2 normal strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.3 weak strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.4.1 i dd current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5 system characteristics for ddr sdrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table of contents .com .com .com .com 4 .com u datasheet data sheet 5 rev. 1.10, 2005-10 hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram table 1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2 ordering information for lead-free(rohs compliant produc ts) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 1 pin configuration of ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4 burst definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6 truth table 1b: dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5 truth table 1a: commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8 truth table 3: current state bank n - command to bank n (same bank) . . . . . . . . . . . . . . . . . . . 52 table 7 truth table 2: clock enable (cke) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 9 truth table 4: current state bank n - command to bank m (different bank). . . . . . . . . . . . . . . . . 54 table 10 truth table 5: concurrent auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 11 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 attention: input and output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 12 electrical characteristics and dc o perating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 table 14 pull-down and pull-up process variations and conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 13 normal strength pull-down and pull-up currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 15 weak strength driver pull-down and pull-up characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 17 ac timing - absolute specificatio ns for ddr400b and ddr333 . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 16 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 17 i dd specification and conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 18 i dd specification for hyb25dc512[800/160c[e/f]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 19 input slew rate for dq, dqs, and dm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 20 input setup & hold time derating for slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 21 input/output setup and hold time de rating for slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 22 input/output setup and hold derating for rise/fall de lta slew rate. . . . . . . . . . . . . . . . . . . . . . . 82 table 23 output slew rate characteristrics ( 8 devices only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 24 output slew rate characteristics ( 16 devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 25 tfbga common package properties (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 list of tables .com .com .com .com 4 .com u datasheet data sheet 6 rev. 1.10, 2005-10 hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram figure 1 pin configuration pg-tfbga-60 (top view) for 8, see the balls throught the package . . . . . . . . 14 figure 2 pin configuration pg-tfbga-60 (top view) for 16, see the balls throught the package . . . . . . . 14 figure 3 pin configuration pg-tsopii-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4 block diagram 512mbit 64 mbit 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5 block diagram 512mbit 32 mbit 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6 required cas latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7 activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8 t rcd and t rrd definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10 read burst: cas latencies (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 11 consecutive read bursts: cas lat encies (burst length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12 non-consecutive read bu rsts: cas latencies (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 13 random read accesses: cas latencies (burst length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . 31 figure 14 terminating a read burst: cas latencies (burst length = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15 read to write: cas latencies (burst length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16 read to precharge: cas latencies (burst length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 17 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 18 write burst (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 19 write to write (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 20 write to write: max. dqss, non- consecutive (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 21 random write cycles (burst length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 22 write to read: non-interrupting (cas latency = 2; burs t length = 4). . . . . . . . . . . . . . . . . . . . . . 42 figure 23 write to read: interrupting (cas latency = 2; burst leng th = 8). . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 24 write to read: min. dqss, odd number of data (3 -bit write), interrupting (cl = 2; bl = 8) . . . . 44 figure 25 write to read: nominal dqss, in terrupting (cas latency = 2; burst length = 8) . . . . . . . . . . . . 45 figure 26 write to precharge: non-interrupting (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 27 write to precharge: interrupting (burst length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 28 write to precharge: min. dqss, odd number of data (1-bit write), interrup ting (bl = 4 or 8) . . . 48 figure 29 write to precharge: nominal dqss (2-bit write), interrupting (burst length = 4 or 8) . . . . . . . . . 49 figure 30 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 31 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 32 clock frequency change in pre charge power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 33 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 34 normal strength pull-down characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 35 normal strength pull-up characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 36 weak strength pull-down characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 37 weak strength pull-up characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 38 ac output load circuit diagram / timing reference load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 39 data input (write), timing burst length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 40 data output (read), timing burst length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 41 initialize and mode register sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 42 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 43 auto refresh mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 44 self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 45 read without auto precharge (burst length = 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 46 read with auto precharge (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 47 bank read access (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 48 write without auto precharge (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 49 write with auto precharge (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 list of figures .com .com .com .com 4 .com u datasheet data sheet 7 rev. 1.10, 2005-10 hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram figure 50 bank write access (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 51 write dm operation (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 52 pullup slew rate test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 53 pulldown slew rate test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 54 package outline p-tfbga-60-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 55 package outline of pg-tsopii-66-1 (green/non-green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 .com .com .com .com 4 .com u datasheet hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram overview data sheet 8 rev. 1.10, 2005-10 09242003-yh6q-tn16 1overview this chapter gives an overview of the 512-mbit double -data-rate sdram product family and describes its main characteristics. 1.1 features ? double data rate architecture: two data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and rece ived with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center-aligned with data for writes ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: 2, 2.5, 3 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? ras-lockout supported t rap =t rcd ?7.8 s maximum average periodic refresh interval ? 2.5 v (sstl_2 compatible) i/o ?v ddq = 2.5 v 0.2 v ?v dd = 2.5 v 0.2 v ? p-tfbga-60 package ? pg-tsopii-66 package ? rohs compliant products 1) 1) rohs compliant product: restriction of the use of ce rtain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercur y, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominat ed biphenyl ethers. table 1 performance part number speed code ?5 ?6 unit speed grade component ddr400b ddr333 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 333 mhz @cl2 f ck2 133 266 mhz .com .com .com .com 4 .com u datasheet data sheet 9 rev. 1.10, 2005-10 09242003-yh6q-tn16 hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram overview 1.2 description the 512-mbit double-data-rate sdram is a high-spe ed cmos, dynamic random-access memory containing 536,870,912 bits. it is internally configured as a quad-bank dram. the 512-mbit double-data-rate sdram uses a double-data -rate architecture to ac hieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pi ns. a single read or write access for the 512-mbit double-data-rate sdram effectively consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide , one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is tran smitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by th e ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 512-mbit double-data-rate sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a pr ogrammed sequence. accesses begin with the registration of an active command, which is th en followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or wr ite burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipelined, multibank archit ecture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all inputs are compatible with the jedec standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the ti ming specifications included in this data sheet are for the dll enabled mode of operation. table 2 ordering information for lead-free(rohs compliant products) part number 1) 1) hyb: designator for memory components 25dc: ddr sdrams at v ddq = 2.5 v 512: 512-mbit density 800/160: product variations x8 and x16 e/f: package type fbga and tsop org. cas-rcd-rp latencies clock (mhz) cas-rcd-rp latencies clock (mhz) speed package hyb25dc512800ce?5 8 3-3-3 200 2.5-3-3 166 ddr400b pg-tsopii-66 hyb25dc512800cf?5 pg-tfbga-60 HYB25DC512160Ce?5 16 pg-tsopii-66 HYB25DC512160Cf?5 pg-tfbga-60 hyb25dc512800ce?6 8 2.5-3-3 166 2-3-3 133 ddr333 pg-tsopii-66 hyb25dc512800cf?6 pg-tfbga-60 HYB25DC512160Ce?6 16 pg-tsopii-66 HYB25DC512160Cf?6 pg-tfbga-60 .com .com .com .com 4 .com u datasheet hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram pin configuration data sheet 10 rev. 1.10, 2005-10 1 pin configuration the pin configuration of a ddr s dram is listed by function in table 1 (60 pins). the abbreviations used in the pin#/buffer# column are explained in table 2 and table 3 respectively. the pin numbering for fbga is depicted in figure 1 and that of the tsop package in figure 2. table 1 pin configuration of ddr sdram ball#/pin# name pin type buffer type function clock signals g2, 45 ck1 i sstl clock signal note: ck and ck are differential cloc k inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). g3, 46 ck1 i sstl complementary clock signal h3, 44 cke i sstl clock enable rank note: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks id le), or acti ve power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power- down. input buffers, excluding cke, are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after v dd is applied on first power up. after v ref has become stable during the power on and initialization sequence, it must be mantained for proper operation of the cke receiver. for proper self-refresh entry and exit, v ref must be mantained to this input. control signals h7, 23 ras i sstl row address strobe g8, 22 cas i sstl column address strobe g7, 21 we i sstl write enable h8, 24 cs i sstl chip select note: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. address signals j8, 26 ba0 i sstl bank address bus 2:0 note: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. j7, 27 ba1 i sstl .com .com .com .com 4 .com u datasheet data sheet 11 rev. 1.10, 2005-10 hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram pin configuration k7, 29 a0 i sstl address bus 11:0 note: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the ba nk is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. l8, 30 a1 i sstl l7, 31 a2 i sstl m8, 32 a3 i sstl m2, 35 a4 i sstl l3, 36 a5 i sstl l2, 37 a6 i sstl k3, 38 a7 i sstl k2, 39 a8 i sstl j3, 40 a9 i sstl k8, 28 a10 i sstl ap i sstl j2, 41 a11 i sstl h2, 42 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: module based on 128 mbit or smaller dies f9, 17 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies data signals 8 organization a8, 2 dq0 i/o sstl data signal bus 7:0 b7, 5 dq1 i/o sstl c7, 8 dq2 i/o sstl d7, 11 dq3 i/o sstl d3, 56 dq4 i/o sstl c3, 59 dq5 i/o sstl b3, 62 dq6 i/o sstl a2, 65 dq7 i/o sstl data strobe 8 organisation e3, 51 dqs i/o sstl data strobe note: output with read data, input with write data. edge-aligned with read data, centered in wr ite data. used to capture write data. data mask 8 organization f3, 47 dm i sstl data mask note: dm is an input mask signa l for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. table 1 pin configuration of ddr sdram ball#/pin# name pin type buffer type function .com .com .com .com 4 .com u datasheet hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram pin configuration data sheet 12 rev. 1.10, 2005-10 data signals 16 organization a8, 2 dq0 i/o sstl data signal 15:0 b9, 4 dq1 i/o sstl b7, 5 dq2 i/o sstl c9, 7 dq3 i/o sstl c7, 8 dq4 i/o sstl d9, 10 dq5 i/o sstl d7, 11 dq6 i/o sstl e9, 13 dq7 i/o sstl e1, 54 dq8 i/o sstl d3, 56 dq9 i/o sstl d1, 57 dq10 i/o sstl c3, 59 dq11 i/o sstl c1, 60 dq12 i/o sstl b3, 62 dq13 i/o sstl b1, 63 dq14 i/o sstl a2, 65 dq15 i/o sstl data strobe 16 organization e3, 51 udqs i/o sstl data strobe upper byte e7, 16 ldqs i/o sstl data strobe lower byte data mask 16 organization f3, 47 udm i sstl data mask upper byte f7, 20 ldm i sstl data mask lower byte power supplies f1, 49 v ref ai ? i/o reference voltage a9, b2, c8, d2, e8, 3, 9, 15, 55, 61 v ddq pwr ? i/o driver power supply a7, f8, m3, m7, 1, 18, 33 v dd pwr ? power supply a1, b8, c2, d8, e2, 6, 12, 52, 58, 64 v ssq pwr ? power supply f2, 34 v ss pwr ? power supply not connected b1, 63 nc nc ? not connected note: 8 organisation b9, 4 nc nc ? not connected note: 8 organization c1, 60 nc nc ? not connected note: 8 organization table 1 pin configuration of ddr sdram ball#/pin# name pin type buffer type function .com .com .com .com 4 .com u datasheet data sheet 13 rev. 1.10, 2005-10 hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram pin configuration c9, 7 nc nc ? not connected note: 8 organization d1, 57 nc nc ? not connected note: 8 organization d9, 10 nc nc ? not connected note: 8 organization e1, 54 nc nc ? not connected note: 8 organization e7, 16 nc nc ? not connected note: 8 organization e9, 13 nc nc ? not connected note: 8 organization f7, 20 nc nc ? not connected note: 8 organization 14, 17, 19, 25, 43, 50 nc nc ? not connected 16 and 8 organization table 2 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 3 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. table 1 pin configuration of ddr sdram ball#/pin# name pin type buffer type function .com .com .com .com 4 .com u datasheet hyb25dc512[800/160]c[e/f] 512-mbit double-data-rate sdram pin configuration data sheet 14 rev. 1.10, 2005-10 figure 1 pin configuration pg-tfbga-60 (top view) for 8, see the balls throught the package figure 2 pin configuration pg-tfbga-60 (top view) for 16, see the balls throught the package 0 3 3 ' & |